1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to improving the performance of shallow junction MOS transistors.
2. Description of the Relevant Art
MOS Circuits are widely used in the electronics industry for an extremely broad range of applications including microprocessors, integrated circuit memories, and applications specific logic products. The basic building block of the MOS integrated circuit is the MOS transistor. FIG. 7 shows a typical embodiment of a single MOS n-channel transistor. MOS transistor 10 includes a lightly doped p-type semiconductor substrate 12, a gate dielectric 16 formed on substrate 12, a conductive gate 14 formed on the gate dielectric, n-type source region 18, and n-type drain region 20. The operation of, and I-V, characteristics of transistor 10 are well known. With no bias applied to conductive gate 14, a reversed bias p-n junction exists between drain region 20 and channel region 22 such that the current flow from drain region 20 to source region 18 is negligible. If, however, a positive bias is applied to conductive gate 14, mobile carriers within channel region 22 of p-type substrate 12 are repelled from the surface leaving behind a depletion region of uncompensated donor ions. If conductive gate 14 is further biased, minority carriers (i.e. electrons) are attracted to channel region 22 of substrate 12 to form a conductive inversion region near the upper surface of semiconductor substrate 12 in channel region 22. The bias required to induce an electron concentration near the surface of substrate 12 approximately equal to the whole concentration in the bulk of semiconductor substrate 12 is referred to as the threshold voltage (V.sub.t). With a threshold voltage V.sub.t applied to conductive gate 14, the conductive channel in channel region 22 permits current flow from drain region 20 to source region 18 if an appropriate bias is applied to drain region 20. For small values of drain voltage V.sub.d (i.e. V.sub.d &lt;V.sub.g -V.sub.t) the current (I.sub.ds) that flows from drain region 20 to source region 18 varies approximately linearly with the drain voltage V.sub.d. For large values of drain voltage (i.e. V.sub.d &lt;V.sub.g -V.sub.t), Ids is independent of V.sub.d to a first order approximation. Applying a gate V.sub.g that is less than the threshold voltage V.sub.t induces a weak inversion region is induced in channel region 22 of semiconductor substrate 12 permitting a small but measurable subthreshold current to flow from source to drain. Subthreshold currents are particularly important in low voltage, low power applications such as MOS integrated circuits because of the large number of transistors in the integrated circuit and because the subthreshold region determines the manner in which the transistors turn on and off.
MOS transistors may be broadly characterized as either short channel or long channel devices. In a long channel device, the sub-threshold current is independent of the drain voltage, the threshold voltage is independent of the channel length and the transistor biasing, and the drain current in the saturation region is independent of the drain voltage. It will be appreciated that these characteristics of long channel devices are desirable from a manufacturing and circuit design perspective because of their tendency to minimize subthreshold currents and threshold voltage variation among transistors of varying dimensions. In contrast to long channel devices, short channel devices are characterized by a subthreshold current that varies with drain voltage, a threshold voltage that varies with channel length and the biasing conditions, and a failure of current saturation in the saturation region. A useful equation has been derived that predicts the minimum channel length which can be expected to result in long channel subthreshold behavior for a given set of process parameters. See, e.g., S. M. Sze., Physics of Semiconductor Devices pp. 431-86 (John Wiley and Sons, 1981). A minimum channel length for long channel operation depends primarily upon the gate oxide thickness, the substrate doping, the drain voltage, and the junction depth of the source/drain regions. Sze, supra, at 471. Other parameters being equal, the minimum channel length for long channel operation varies with the cube root of the junction depth. As the channel length of MOS transistors has been reduced through advancements in photolithography and other semiconductor processing techniques, the significance of the subthreshold characteristics and the efforts to minimize subthreshold effects have been correspondingly increased. Unfortunately, the conventional methods of forming source region 18 and drain region 20 of transistor 10 has provided a source of frustration for process designers attempting to minimize short channel effects. Typically, source region 18 and drain region 20 of transistor 10 are fabricated by an ion implantation technique in which ions of appropriate impurities, or boron are implanted into semiconductor substrate 12. Even when used in conjunction with a dielectric layer formed on the surface prior to the implantation, the ion implantation process typically results in a junction depth x that places a lower limit on the minimum channel device that can be fabricated with long channel characteristics. In addition, processing subsequent to the ion implantation process typically redistributes the ion implantation distributions such that the as implanted junction depth is less than the junction depth that exists at the completion of the fabrication process. Accordingly, efforts to minimize short channel effects in MOS transistors in the submicron range have been greatly constrained by the minimum junction depth x typically available with the standard MOS transistor formation process. It would therefore be highly desirable to implement a fabrication process in which the junction depth of the MOS transistor could be significantly reduced without undesirably altering other transistor parameters.